1. Field of the Invention
The present invention relates to a method for providing metallization patterns on a very-large scale or wafer-scale integrated circuit.
2. The Prior Art
A wafer-scale integrated circuit can be defined in a whole wafer of active circuits mounted in a single package. A large number of usually identical, separately functional integrated circuits are provided on a single semiconducting wafer. Certain electrical connections known as global connections are common to all or most of the integrated circuits. Power connections and connections carrying common control signals are suitable subjects for global treatment. Any signal which is provided simulataneously to a substantial proportion of the integrated circuits on the wafer is global. The extensiveness of the distribution of global signals necessitates their distribution via a network of metal conductor paths to minimise losses.
In the present state-of-the-art there exist two methods for making the metallization pattern required for the manufacture of a wafer-scale integrated circuit. In a first method one mask is used which is common to all of the individual integrated circuits on the wafer. The mask is used first in one position on the wafer, then in another, to mark out on the wafer a repetetive plurality of metal areas on the wafer, each area corresponding to the metallization pattern of an individual integrated circuit. This process is known as "step and repeat", that is the same pattern being repeated at controlled intervals across the wafer. The metal areas for each of the integrated circuits can include Global lines, in which case the disposition and necessary repetitive symmetry of these connections place severe limitations on the manner in which the Global connections can be made. It is more usually the case that the metal areas for the individual integrated circuits are laid down as a first pattern of metallization, and interconnections between the individual integrated circuits are laid down as a second pattern of metallization. This necessitates a cost and time consuming two pass metallization process.
In a second method a reticle can be used, that is, a mask which covers all or most of the area of the wafer. The metalisation pattern both within each of the integrated circuits on the wafer and therebetween is laid down as a single process.
In this second method a first problem arises concerning the positional accuracy which can be defined by a reticle. While the step-and-repeat method currently allows for the definition of position on the wafer and consequent control of conductor dimensions to within around 2 micrometers, the use of a reticle, which can be generated only as accurately as the pattern generator which creates it, allows only that a position on the wafer be defined with an accuracy of the order of 10 micrometers. This five-to-one loss of definition in conductor positions and dimensions necessitates that the individual integrated circuits on the wafer be much more loosely packed with components than might otherwise be possible using a step-and-repeat metalising masking process. The loss of Areal efficiency so encountered makes the use of a single reticle metallization masking process for a wafer-scale integrated circuit most unattractive.
A second problem arises with the second method in that, while it is relatively easy to align a step-and-repeat small area mask over a wafer, it is extremely difficult and time consuming and requires much skill to so align a reticle which bears individual circuit detail.